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| February 1997 NDS352AP P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description These P -Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, portable electronics, and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package. Features -0.9 A, -30 V. RDS(ON) = 0.5 @ VGS = -4.5 V RDS(ON) = 0.3 @ VGS = -10 V. Industry standard outline SOT-23 surface mount package using proprietary SuperSOTTM-3 design for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. ________________________________________________________________________________ D G S Absolute Maximum Ratings Symbol VDSS VGSS ID Parameter Drain-Source Voltage T A = 25C unless otherwise noted NDS352AP -30 20 (Note 1a) Units V V A Gate-Source Voltage - Continuous Maximum Drain Current - Continuous - Pulsed 0.9 10 PD TJ,TSTG Maximum Power Dissipation (Note 1a) (Note 1b) 0.5 0.46 -55 to 150 W Operating and Storage Temperature Range C THERMAL CHARACTERISTICS RJA RJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) (Note 1) 250 75 C/W C/W (c) 1997 Fairchild Semiconductor Corporation NDS352AP Rev.D Electrical Characteristics (TA = 25C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS IDSS Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = -250 A VDS = -24 V, VGS = 0 V TJ =125C IGSSF IGSSR Gate - Body Leakage, Forward Gate - Body Leakage, Reverse VGS = 20 V, VDS = 0 V VGS = -20 V, VDS = 0 V -30 -1 -10 100 -100 V A A nA nA ON CHARACTERISTICS (Note 2) VGS(th) RDS(ON) Gate Threshold Voltage VDS = VGS, ID = -250 A TJ =125C Static Drain-Source On-Resistance VGS = -4.5 V, ID = -0.9 A TJ =125C VGS = -10 V, ID = -1 A ID(ON) gFS Ciss Coss Crss td(on) tr td(off) tf td(on) tr td(off) tf On-State Drain Current VGS = -4.5 V, VDS = -5 V VDS = -5 V, ID = -0.9 A VDS = -15 V, VGS = 0 V, f = 1.0 MHz -2 1.9 -0.8 -0.5 -1.7 -1.4 0.45 0.65 0.25 -2.5 -2.2 0.5 0.7 0.3 A S V Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance DYNAMIC CHARACTERISTICS 135 88 40 pF pF pF SWITCHING CHARACTERISTICS (Note 2) Turn - On Delay Time Turn - On Rise Time Turn - Off Delay Time Turn - Off Fall Time Turn - On Delay Time Turn - On Rise Time Turn - Off Delay Time Turn - Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = -10 V, ID = -0.9 A, VGS = -4.5 V VDD = -10 V, ID = -1 A, VGS = -10 V, RGEN = 50 VDD = -6 V, ID = -1 A, VGS = -4.5 V, RGEN = 6 5 17 35 30 10 30 70 60 ns ns ns ns ns ns ns ns nC nC nC 8 16 35 30 2 0.5 1 15 30 90 90 3 Qg Qgs Qgd NDS352AP Rev.D Electrical Characteristics (TA = 25C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS ISM VSD Notes: 1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RCA is determined by the user's board design. Maximum Continuous Source Current Maximum Pulsed Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage VGS = 0 V, IS = -0.42 (Note 2) -0.8 -0.42 -10 -1.2 A A V PD (t) = T J -T A R JA(t) = T J -T A R JC +R CA(t) = I 2 (t) x R DS(ON)@T J D Typical RJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 250oC/W when mounted on a 0.02 in2 pad of 2oz copper. b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper. 1a 1b Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%. NDS352AP Rev.D Typical Electrical Characteristics -5 I D , DRAIN-SOURCE CURRENT (A) 1.6 DRAIN-SOURCE ON-RESISTANCE VGS = -10V -7.0 -6.0 -5.5 R DS(on), NORMALIZED V GS = -3.5 V 1.4 1.2 1 0.8 0.6 0.4 -4 -5.0 -4.5 -4.0 -4.0 -4.5 -5.0 -5.5 -6.0 -7.0 -10 -3 -2 -3.5 -1 -3.0 0 -1 V DS 0 -2 -3 -4 -5 0 -1 , DRAIN-SOURCE VOLTAGE (V) -2 -3 I D , DRAIN CURRENT (A) -4 -5 Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.6 1.6 I D = -0.9A R DS(on), NORMALIZED DRAIN-SOURCE ON-RESISTANCE DRAIN-SOURCE ON-RESISTANCE 1.4 V GS = -4.5V 1.4 1.2 1 0.8 0.6 0.4 TJ = 125C 25C R DS(ON), NORMALIZED 1.2 1 -55C 0.8 V GS = -4.5V 0.2 0 -1 -2 I D , DRAIN CURRENT (A) -3 -4 0.6 -50 -25 0 25 50 75 100 T J , JUNCTION TEMPERATURE (C) 125 150 Figure 3. On-Resistance Variation with Temperature. Figure 4. On-Resistance Variation with Drain Current and Temperature. V DS = -10V -3.2 T = -55C J 25 125 GATE-SOURCE THRESHOLD VOLTAGE -4 1.2 I , DRAIN CURRENT (A) 1.1 -2.4 1 -1.6 0.9 D -0.8 0.8 -1 -2 -3 -4 -5 V GS , GATE TO SOURCE VOLTAGE (V) -6 0.7 -50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (C) Figure 5. Transfer Characteristics. Figure 6. Gate Threshold Variation with Temperature. NDS352AP Rev.C Typical Electrical Characteristics (continued) 1.1 4 DRAIN-SOURCE BREAKDOWN VOLTAGE VGS = 0V -I , REVERSE DRAIN CURRENT (A) ID = -250A 1 1.08 1.06 1.04 1.02 1 0.98 0.96 0.94 -50 T J = 125C 0.1 BV DSS , NORMALIZED 25C -55C 0.01 0.001 -25 0 25 50 75 100 T J , JUNCTION TEMPERATURE (C) 125 150 S 0.0001 0 0.2 0.4 0.6 0.8 1 1.2 -V SD , BODY DIODE FORWARD VOLTAGE (V) 1.4 Figure 7. Breakdown Voltage Variation with Temperature. Figure 8. Body Diode Forward Voltage Variation with Source Current and Temperature. 400 10 , GATE-SOURCE VOLTAGE (V) 300 200 ID = -0.9A 8 VDS = -5V -10 -15 Ciss CAPACITANCE (pF) 100 Coss 6 4 50 Crss f = 1 MHz V GS = 0 V 2 30 20 0 .1 -V 0 .2 -V 0 .5 1 2 5 10 , DRAIN TO SOURCE VOLTAGE (V) 20 30 GS 0 0 1 Q g 2 3 4 5 DS , GATE CHARGE (nC) Figure 9. Capacitance Characteristics. Figure 10. Gate Charge Characteristics. VDD t d(on) ton tr 90% t off t d(off) 90% tf VIN D RL V OUT VOUT 10% VGS R GEN 10% 90% G DUT S V IN 10% 50% 50% PULSE WIDTH INVERTED Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms. NDS352AP Rev.C Typical Electrical Characteristics (continued) , TRANSCONDUCTANCE (SIEMENS) 3 20 V DS = - 5V -I D , DRAIN CURRENT (A) 2.5 10 5 2 1 0.5 RD S(O N) LI 1m s T MI TJ = -55C 2 1.5 1 0.5 0 0 -1 D 10m s 25C 125C 10 0m s 1s 0.1 0.05 g FS VGS = -4.5V SINGLE PULSE R JA = See Note 1b A T = 25C A 0.2 0.5 1 2 5 10s DC -2 -3 -4 -5 0.01 0.1 10 20 30 50 I , DRAIN CURRENT (A) - VDS , DRAIN-SOURCE VOLTAGE (V) Figure 13. Transconductance Variation with Drain Current and Temperature. Figure 14. Maximum Safe Operating Area. STEADY-STATE POWER DISSIPATION (W) -ID , STEADY-STATE DRAIN CURRENT (A) 1 1.2 1.1 1 0.9 0.8 0.7 0.6 0 0.1 0.2 0.3 2 0.8 0.6 1b 1a 1a 0.4 1b 4.5"x5" FR-4 Board o TA = 25 C Still Air V = -4.5V GS 0.2 4.5"x5" FR-4 Board o TA = 25 C Still Air 0 0 0.1 0.2 0.3 0.4 2oz COPPER MOUNTING PAD AREA (in2 ) 0.4 2oz COPPER MOUNTING PAD AREA (in ) Figue 15. SuperSOTTM _ 3 Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. Figure 16. Maximum Steady-State Drain Current versus Copper Mounting Pad Area. 1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.0001 D = 0.5 0.2 0.1 0.05 0.02 0.01 Single Pulse R JA (t) = r(t) * R JA R JA = See Note 1b P(pk) t1 t2 TJ - TA = P * R JA (t) Duty Cycle, D = t1 /t2 0.001 0.01 0.1 t 1 , TIME (sec) 1 10 100 300 Figure 17. Transient Thermal Response Curve. Note : Characterization performed using the conditions described in note 1b. Transient thermal response will change depending on the circuit board design. NDS352AP Rev.C |
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